- Comparison Between 8086 80286 80386 80486 And Pentium Microprocessor
- Comparison Between 8086 80286 80386 80486 And Pentium All In One
- Comparison Between 8086 80286 80386 80486 And Pentium I7
- Comparison Between 8086 80286 80386 80486 And Pentium Processors
- The Intel 80286 (also marketed as the iAPX 286 and often called Intel 286) is a 16-bit microprocessor that was introduced on February 1, 1982. It was the first 8086-based CPU with separate, non-multiplexed address and data buses and also the first with memory management and wide protection abilities.
- 9 The 8086, 80286, 80386, 80486, and Pentium Microprocessor Q46: What are the three elements that can be used to form the effective address of an operand in memory? Write its general formula. A: Base, index, and displacement; EA=Base + Index + Displacement. Q47: Name the five memory operand addressing modes.
COMPARISON OF PENTIUM PROCESSOR WITH 80386 AND 80486 PROCESSOR’S LIMITATIONS OF 80286 THAT LEAD TO 6 has only a 16 bit processor. Maximum segment size of 80286 is 64 KB. 80286 cannot be easily switched between real mode and protected mode because resetting was required. The amount of memory addressable by the 80286 is 16M byte.
80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit operation in one cycle. It has data and address bus of 32-bit each. Thus has the ability to address 4 GB (or 232) of physical memory.
Comparison Between 8086 80286 80386 80486 And Pentium Microprocessor
Multitasking and protection capability are the two key characteristics of 80386 microprocessor. 80386 has an internal dedicated hardware that permits multitasking.
We know 8086 is a 16-bit microprocessor and 80286 was an advancement of 8086 with some additional characteristics. But with the advent of technology intel introduced a 32-bit microprocessor whose processing speed was twice as that of 80286 microprocessor.
This was 80386 microprocessor that was designed by Intel in October 1985 and was an upgraded version of 80286 microprocessor.
Features of 80386
- As it is a 32-bit microprocessor. Thus has 32-bit ALU.
- 80386 has data bus of 32-bit.
- It holds address bus of 32 bit.
- It supports physical memory addressability of 4 GB and virtual memory addressability of 64 TB.
- 80386 supports variety of operating clock frequency, which are 16 MHz, 20 MHz, 25 MHz and 33 MHz.
- It offers 3 stage pipeline: fetch, decode and execute. As it supports simultaneous fetching, decoding and execution inside the system.
Operating modes of 80386
We have already discussed in our previous article that 80286 supports two operating modes. The first is real address mode while the second is the protected virtual address mode. However, 80386 supports 3 operating modes: real, protected and virtual real mode.
Of the two modes of 80286 microprocessor, initially the 80286 was booted in real mode. However, to have better operating performance, separate software command is used to switch from the real mode to the protected mode.
But it requires the resetting of microprocessor in order to switch to real mode from protected mode. This drawback was eliminated in 80386 that allows the switching between the modes using software commands.
In the protected mode, 80386 microprocessor operates in similar way like 80286, but offers higher memory addressing ability.
In virtual mode, the overall memory of 80386 can be divided into various virtual machines. And all of them acts as a separate computer with 8086 microprocessor. This mode is also called virtual 8086 mode or V86 mode.
The other one is the virtual real mode, this mode allows the system to execute multiple programs in the protected memory. And in case a program at a particular memory gets crashed then it will not cause any adverse effect on the other part of the memory.
Architecture of 80386 Microprocessor
The figure below shows the architectural representation of 80386 microprocessor:
Basically it has 6 functional units which are as follows:
- Bus Interface Unit
- Code Fetch Unit
- Instruction Decode Unit
- Execution Unit
- Memory Management Unit
As we have already discussed that the 80386 possess the ability of 3 stage pipelining thus performs fetching, decoding and execution simultaneously along with memory management and bus accessing. Thus all these units operate parallely.
This pipelining technique leads to reduction in overall processing time thereby increasing the performance of the overall system.
Let us now move further and understand the operation of each unit in detail.
1. Bus Interface Unit
The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as 32-bit address bus. Whenever a need for an instruction or a data fetch is generated by the system then the BIU generates signals (according to the priority) for activating the data and address bus in order to fetch the data from the desired address.
The BIU connects the peripheral devices through the memory unit and also controls the interfacing of external buses with the coprocessors.
2. Code Prefetch Unit
This unit fetches the instructions stored in the memory by making use of system buses. Whenever the system generates a need for an instruction then the code prefetch unit fetches that instruction from the memory and stores it in 16-byte prefetch queue.
So to speed up the operation this unit fetches the instructions in advance and the queue stores these instructions.
The sequence in which the instructions are fetched and gets stored in the queue depends on the order they exist in the memory.
As this unit fetches one double word in single access. So, in such a case, it is not necessary that each time only a single instruction will be fetched, as the fetched instruction can be parts of two different instructions.
It is to be noted here that, code prefetching holds lower priority than data transferring. As whenever, a need for data transfer is generated by the system then immediately the code prefetcher leaves the control over the buses. So that the BIU can transfer the required data.
But prefetching of instruction and storing it in the queue reduces the wait for the upcoming instruction to almost zero.
3. Instruction Decode Unit
We know that instructions in the memory are stored in the form of bits. So, this unit decodes the instructions stored in the prefetch queue. Basically the decoder changes the machine language code into assembly language and transfers it to the processor for further execution.
4. Execution Unit
The decoded instructions are stored in the decoded instruction queue. So, these instructions are provided to the execution unit in order to execute the instructions.
The execution unit controls the execution of the decoded instructions. This unit has a 32-bit ALU, that performs the operation over 32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8 special purpose registers. These are used for data handling and calculation of offset address.
5. Memory Management Unit
This unit has two separate units within it. These are
- Segmentation Unit and
- Paging Unit
Segmentation unit: The segmentation unit plays a vital role in the 80836 microprocessor. It offers protection mechanism in order to protect the code or data present in the memory from application programs.
It gives 4 level protection to the data or code present in the memory. Every information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the highest priority and PL3 holds the lowest priority.
Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0. Then only those programs which are working at PL0 would be able to access that file. While other programs will not be able to access the same.
Also, if a file is present at PL1, then programs of PL0 and PL1 both can access it. As PL0 has higher priority than PL1. So, for protection purpose the main part of OS is stored in PL0 while PL3 holds the user programs.
Providing protection to the data or code inside the system is the most advantageous factor that was first given by 80386 microprocessor.
Paging Unit: The paging unit operates only in protected mode and it changes the linear address into physical address. As the programmer only provides the virtual address and not the physical address.
The segmentation unit controls the action of paging unit, as the segmentation unit has the ability to convert logical address into linear address at the time of executing an instruction.
Basically it changes the overall task map into pages and each page has a size of 4K. This allows the handling of task in the form of pages rather than segments.
Paging unit supports multitasking. This is so because the physical memory is not required to hold the whole segment of any task. Despite, only that part of the segment which is needed to be currently executed must be stored in that memory whose physical address is calculated by the paging unit.
This resultantly reduces the memory requirement and hence this frees the memory for other tasks. Thus by this we get an effective way for managing the memory to support multitasking.
This is all about the architecture of 80386 microprocessor.
A noteworthy point over here is that 80386 has 2 different versions. These are 80386SX and 80386DX. The SX stands for single execution while the DX stands for double execution.
Comparison Between 8086 80286 80386 80486 And Pentium All In One
80386SX holds a data bus of 16-bit. While 80386DX has a data bus of 32-bit.
Whenever we talk about 80386 then it nothing but 80386DX having 32-bit data bus. But sometimes a system having 8086 microprocessor needs to improve the its performance as well as protection. And we know that 8086 is a 16-bit microprocessor, that operates on 2 banks.
But 80386 in general has a 32-bit data bus that needs 4 banks. So, to access some of the features of 80386 in a system having 8086 processor, we use 80386SX as processor having data bus of 16-bit.
Thus in this case, a system can be upgraded to facilities of 80386 by simply changing the processor despite changing the overall system. This is reason why we have 80386SX version of the 80386 microprocessor.
Comparison Between 8086 80286 80386 80486 And Pentium I7
Generally, we consider 80386 as 80386DX, a processor with 32-bit of data bus.
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Comparison Between 8086 80286 80386 80486 And Pentium Processors
LIMITATIONS OF 80286 THAT LEAD TO 80386
80286 has only a 16 bit processor.
Maximum segment size of 80286 is 64 KB.
80286 cannot be easily switched between real mode and protected mode because resetting was required.
The amount of memory addressable by the 80286 is 16M byte.
To increase the over all system performance.
THE 80386 MICROPROCESSOR
A 32-bit microprocessor introduced by Intel in 1985.
The chip of 80386 contains 132 pins.
It has total 129 instructions.
It has 32 bit data bus 32 bit address bus.
The execution of the instructions is highly pipelined and the processor is designed to operate in a multiuser and multitasking.
Software written for the 8088,8086,80186 and 80286
will also run on 386.
The address bus is capable of addressing over 4 gigabytes of physical memory.
Virtual addressing pushing this over 64 terabytes of storage.
80387 coprocessor is used.
The processor can operate in two modes:
In the real mode physical address space is 1Mbytes and maximum size of segment is 64KB.
In the protected mode address space is 4G bytes and maximum size of segment is upto entire physical addressing space.
80386 processor is available in 2 different versions.
386DX
32 bit address bus and 32 bit data bus.
132 pins package.
386SX
24 bit address bus and 16 bit data bus.
100 pin package.
The lower cost package and ease of interfacing 8 bit and 16 bit memory and peripherals.
But the address range and memory transfer rate are lower than that of 386DX.
REGISTER SET-80386
It included all eight general purpose registers plus the
four segment registers.
The general purpose registers were 16 bit wide in earlier machines, but in 386 these registers can be extended to 32 bit.
Their new names are EAX,EBX,ECX and so on.
Two additional 16 bit segment are included FS and GS.
MEMORY SYSTEM OF THE 80386 The memory bank are accessed via four bank enable signals BE0,BE1,BE2 and BE3. Bank3
1G*8
Bank 2
Bank1
1G*8
1G*8
Bank 0
1G*8
32 bit
BE0,BE1,BE2 and BE3 are active low signals.
THE 80486 MICROPROCESSOR
80486 is the next in Intel’s upward compatible 80x86
architecture.
Only few differences between the 80486 and 80386, but these differences created a significant performance improvement.
32 bit microprocessor and same register set as 80386.
Few additional instructions were added to its instruction set.
4 gigabyte addressing space .
IMPROVEMENTS MADE IN 80486 OVER 80386
80486 was powered with a 8KB cache memory.
This improved the speed of 80486 processor to great extent.
Some new 80486 instructions are included to maintain the cache.
It uses four way set associative cache.
80486 also uses a co-processor similar to 80387 used with 80386.
But this co-processor is integrated on the chip allows it to execute instructions 3 times faster as 386/387 combination.
The new design of 80486 allows the instruction to execute with fewer clock cycles.
486 is packed with 168 pin grid array package instead of the 132 pin used for 386 processor.
This additional pin’s made room for the additional signals.
This new design of 80486 allows the instruction to
execute with fewer clock cycles.
These small differences made 80486 more powerful processor.
THE PENTIUM PROCESSOR
WHY THE NAME PENTIUM ?????
Intel wanted to prevent their competitors from branding their processors with similar names, as AMD had done
with their Am486.
The name Pentium is originally derived from the Greek word pente meaning 'five' as the series was Intel's 5th generation microarchitecture.
THE PENTIUM PROCESSOR
Upward compatibility has been maintained.
It can run all programs written for any 80x86 line, but does so at a double the speed of fastest 80486.
Pentium is mixture of both CISC and RISC technologies.
All the prior 80x86 processor are considered as CISC processor.
The addition of RISC aspects lead to additional performance improvement.
It uses 64 bit data bus to address memory organized in 8 banks, each bank contains 512 MB of data. Each bank can store a byte of data.
BE7
BE6
BE5
BE4
BE3
B7
B6
B5
B4
B3
BE2
BE1
BE0
B2
B1
B0
64 bit
Memory System of Pentium
All these bank enable signals are active low.
IMPROVEMENTS OF PENTIUM OVER 80X86
Separate 8KB data and instruction cache memory.
Dual Integer pipelines are present but only single integer pipeline is present in 80486.
Branch Prediction Logic.
CACHE MEMORY
The Pentium contains two 8K-byte cache.
An 8 byte instruction cache, which stores the instruction.
An 8 byte data cache, stores the data used by the instructions.
In the 80486 with unified cache, a program that was data intensive quickly fills the cache, allowing less room for instructions.
In Pentium this cannot occur because of the separate instruction cache.
PIPELINING
It is a technique used to enable one instruction to complete with each clock cycle.
In Pentium there are two instruction pipelines, the U pipeline and V pipeline.
These pipelines instructions.
During Execution the U and V pipelines are capable of executing two integer instructions at the same time and one floating point instructions.
are
responsible
for
executing
80x86
PIPELINING F
D
I1
I1
2
Clock Cycle 1
F
I1
D
E
F
D
E
F
D
E
I1
I2
I2
I2
I3
I3
I3
3
4
5
6
7
I2
I3
I4
I5
I1
I2
I3
I4
E Clock Cycle
1
2
I1
I2
I3
3
4
5
8
9
On a non pipelined machine 9 clock cycles are needed for the individual fetch, decode and execute cycle.
On a pipelined machine fetch, decode and execute operations are performed in parallel only 5 cycles are needed to execute the same three instructions.
The First instructions needed 3 cycles to complete.
Additional instructions complete at rate of 1 per cycle.
The Instruction pipelines are five-stage pipelines and capable of independent operations.
The Five-Stages are, PF – PreFetch D1 – Instruction Decode D2 – Address Generate EX - Execute Cache and ALU Access. WB – Write Back
The U pipeline can execute any processor instruction where as V pipeline only execute Simple Instruction.
BRANCH PREDICTION LOGIC
The purpose of branch prediction logic is to reduce the time required for a branch caused by internal delays.
The microprocessor begins pre-fetch instruction at the branch address.
The instructions are loaded into the instruction cache.
When the branch occurs, the instruction are present and allow the branch to execute in one clock period.
If the branch prediction logic errs, the branch requires an extra three clock cycles.
SPEED OF PROCESSORS The 80286 - 25 MHz The 80386 - 40MHz The 80486 - 60 MHz The Pentium -90 MHz
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